- “Sub-Sampling Wireless RX”
- Taped-out in May 2019
- “8‐bit Ultra‐Low‐Power SAR ADC for Bio-signals”
- Taped-out in August 2018
- “A 75-dB 100-MHz Signal-Bandwidth Continuous-Time Delta-Sigma ADC”
- Built system-level simulations using both VerilogA and Matlab for CIFF and CIFB architectures.
- Built 1.5bit Quantizer and 1.5bit Feedback DAC.
- “A Low‐Power 12‐Gbps Multi‐Standard SERDES Transceiver” (Funded by ITIDA)
- Designed an ultra‐low‐power ADC and a Discrete-Time Linear Equalizer (DTLE).
- Modeled a Digital DFE and an adaptive CTLE
- Finished post‐layout simulations for 20‐Gbps 15.5-mW ADC in UMC65 and built the chip I/O Pad ring.
- “High‐Speed Serial Link Transceiver for 10Gbase‐KR Standard Using a 65‐nm CMOS Process”
- Modeled a time‐interleaved Flash ADC using Matlab Simulink
- Designed a 4‐bit 10GS/s time-interleaved Flash ADC, Thermometer to binary digital encoder, and 1:16 Demultiplexer.
- Designed the digital RX system level.
- “Zero/Low IF Wireless Receiver Frontend: LNA + Harmonic‐Reject Quadrature Mixer”
- Ongoing design
- “12‐bit 200‐MS/s 5‐GHz Bandwidth Track and Hold Circuit”
- Ongoing design
- “An Inductor‐less Wideband Low Noise Amplifier”
- Designed a Gm‐boosted LNA using feedforward cancellation technique.
- Designed for low‐gain and high‐gain operation.
- “A Rail‐to‐Rail Input / Output Current‐Recycling Folded Cascode OTA in 45nm Process”
- Designed a two‐stage OTA with a rail‐to‐rail input and output.
- Used miller and feedforward compensation.
- “A Design of eDRAM System Architecture”
- Designed 4T and 3T1D eDRAM cells, Sense Amplifier, Column Tree Decoder, and NOR Row Decoder.
- Used Fin‐FET Verilog‐A model from EECS Berkeley open library.
- “A Design of Full 6‐Gbps SERDES Link: Channel‐Characterization, TX and RX”
- Designed CTLE, VGA, Sampler and SR Latch.
- “A Design of SC Buck DC‐DC Step‐Down Converter”
- Designed Multi‐ratio (1, 3/4, 2/3, 4/5) adaptive SC DC‐DC converter to down convert 2.5V nominal line to 1.8V
- 38mV output ripples for 200mV input ripples, 30mΩ ESR and accuracy of 20mV
- “A Design of Wideband Low‐Noise Amplifier (LNA)”
- Designed a highly linear LNA with 18.25dB gain, 1dB NF, 2.2dBm IIP3.
- The total power consumption is 4.3mA. The LNA is operating from 200MHz to 2.45GHz
- “Designing a Spiral, Coplanar and Microstrip Inductors Using Sonnet”
- Designed different types of integrated inductors with different quality factors.
- Gained experience in Sonnet software.
- “A Model of a Simple System Level for Bluetooth System Using Simulink”
- Modeled a simple and abstractive Bluetooth system using ADC and Phase domain ADC.
- “Design and Characterization of a CMOS 8‐bit Microprocessor Data Path”
- Designed the behavioral model of an 8‐bit microprocessor using Verilog.
- Designed the barrel shifter, latches and flip‐flops & their layout using L‐Edit.
- “System Level Design of a Pipeline ADC”
- Modeled a 1.5bit M‐DAC based Pipeline ADC using Matlab Simulink.
- Investigated building open‐loop and closed‐loop amplifier in each pipeline sub‐stage.
- “Behavioral Modeling for Serial Data Receiver Using VHDL”
- Designed a behavioral serial data RX that receives data chunks of 10 bits from a serial data bus.
- RX was modeled Using Xilinix, Modelsim and written in VHDL.
- Rectenna RF-DC Conversion.
- Design and Characterization of a CMOS 8‐bit Microprocessor Data Path (VLSI course – 4th year)
- Temperature control and alarm system using AVR Microcontroller (Embedded systems course- 4th year)
Image Compression by Matlab. (DSP course- 4th year)
White, Survey paper entitled “General Applications on Biomedical Acoustics” – (Acoustics course- 3rd year)
Probability and its Relation to Quantum mechanics (Probability course- 2nd year)
Serial Data Receiver (Digital Design II course – 2nd year)
“LED Matrix Display” using logic gates (Logic Design course – 1st year)